![digital logic - SR Latch: Why reverse S and R in NAND and NOR if it reverses the outputs too? - Electrical Engineering Stack Exchange digital logic - SR Latch: Why reverse S and R in NAND and NOR if it reverses the outputs too? - Electrical Engineering Stack Exchange](https://i.stack.imgur.com/og9PY.png)
digital logic - SR Latch: Why reverse S and R in NAND and NOR if it reverses the outputs too? - Electrical Engineering Stack Exchange
Latches and flip flops Sequential Circuits The combinational circuit does not use any memory. Hence the previous state of input
![a) SR latch using NOR gates (b) C17 benchmark circuit using NAND gates... | Download Scientific Diagram a) SR latch using NOR gates (b) C17 benchmark circuit using NAND gates... | Download Scientific Diagram](https://www.researchgate.net/publication/326669247/figure/fig3/AS:653327951998978@1532776930320/a-SR-latch-using-NOR-gates-b-C17-benchmark-circuit-using-NAND-gates-Tables-IV-and-V.png)
a) SR latch using NOR gates (b) C17 benchmark circuit using NAND gates... | Download Scientific Diagram
![Digital Lab - S-R Latch With Enable Input using NAND Gates | Digital IC Projects | Electronics Textbook Digital Lab - S-R Latch With Enable Input using NAND Gates | Digital IC Projects | Electronics Textbook](https://www.allaboutcircuits.com/uploads/articles/gated-S-R-latch-circuit-diagram.jpg)